Gee!
First attempt to compile a design from a button, flip-flop and LED on #Tangmega138k. Clock wire routing failed. 馃ぃ
We'll look into what the problem is.
#fpga#apicula#sipeed#gowin
1
Gee!
First attempt to compile a design from a button, flip-flop and LED on #Tangmega138k. Clock wire routing failed. 馃ぃ
We'll look into what the problem is.
#fpga#apicula#sipeed#gowin
@yrabbit Time to go to asynchronous logic 馃榿