This #FPGA passes the finger test. It doesn’t get burning hot when no bitstream is loaded!
The last one’s IO banks must have been blasted short or something. That thing got hot immediately.
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This #FPGA passes the finger test. It doesn’t get burning hot when no bitstream is loaded!
The last one’s IO banks must have been blasted short or something. That thing got hot immediately.
1
And we have JTAG! OpenFPGALoader doesn't know about this Virtex US+ #FPGA though. Let's see what Vivado says.
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@craigjb I don't think OpenFPGALoader can handle any of the multi-SLR parts due to the longer JTAG IR even if it knew the IDCODE. I need to get my Jaytag library and tool to a point it's ready for public consumption. It knows everything that has a BSDL shipped with ISE or Vivado and a few that don't, should be able to load anything not Versal or XCSU+.